A signal converter circuit can convert input signals having a particular convention (e.g., shape, amplitude, number of phases, and/or offset) for use by other circuits that require a different signal convention. One type of conversion can be from two differential input signals into one single swing output signal.
To better understand various features of the disclosed embodiments, conventional approaches to converting differential input signals into a single ended output signal will first be described.
A conventional solution for differential to single-ended signal conversion can utilize a differential pair based comparator. For example, a conventional differential complementary metal-oxide-semiconductor (CMOS) or bipolar transistor based differential comparator can be used to detect when two differential input signals vary from one another. Such conventional solutions are typically designed to function with differential signals having a crossing point at or near a midpoint between a maximum and minimum voltage of the input signals. Such a constraint can arise as differential pair based comparators typically operate within a finite common-mode voltage range.
Differential signals can take various forms, and can include “latched” differential signals. Latched differential signals can be two signals that vary between a maximum signal value and minimum signal value in the same general time frame. Thus, at the time one signal transitions from high-to-low, the other signal can be transitioning from low-to-high.
In some cases, latched differential signals can have crossing points near either the minimum or maximum signal value. Examples of such signal crossings are shown in FIGS. 13A and 13B. Both FIGS. 13A and 13B are timing diagrams showing two signals VIN+ and VIN− that can vary between a maximum voltage VHIGH and a minimum voltage VLOW. FIG. 13A shows a signal crossing point close a minimum voltage VLOW. FIG. 13B shows a signal crossing point close to a maximum voltage VHIGH.
When differential signals have such low or high crossing points, the signals can be outside the input voltage range of a conventional differential pair based comparator input as they drive to either the positive or negative supply voltages. In addition, such signals may not exhibit sufficient differential voltage to fully switch output states (high, low) of a conventional differential to single ended signal converter.
One type of circuit that can generate latched differential signals can be a particular class of oscillators that generate differential oscillating signals via a pair of cross-coupled latches. Such latches are typically have a NAND or NOR latch configuration. In particular, n-type field effect transistor (NFET) or p-type field effect transistor (PFET) logic implementations of a NAND or NOR latch oscillator architecture can generate latched differential output signals, such as those shown in FIGS. 13A and 13B. In such arrangements, VHIGH can be a positive supply voltage and/or max swing voltage and VLOW can be a negative supply voltage and/or minimum swing voltage.
Example delay cells that can be used in oscillator circuits are shown in U.S. patent application Ser. No. 11/415,588, filed on May 1, 2006, titled VOLTAGE CONTROLLED OSCILLATOR DELAY CELL AND METHOD by Sividasan et al.
Conventional differential to single ended solutions that rely on differential sensing may not be suitable for use with latched differential signals like those described above. In particular, as noted above, attempts to convert such latched differential signals may not work due to the common-mode input voltage being out of range. In addition, when such circuits do detect a change in such differential input signals, errors in determining the correct switching point can occur, resulting in duty cycle distortion and/or conversion timing jitter in the corresponding single ended output signal.